AI generates wiring diagrams, full BOMs, and assembly guides from a single prompt
A publicly available tool, published in April 2026, uses Claude Opus 4.7 to design physical electronics from a text description: it produces the schematic, the complete bill of materials, and a step-by-step assembly guide. No CAD seat required. No EDA apprenticeship required. The generated output is functional — this was demonstrated with working Arduino and Raspberry Pi builds.
The three tasks that traditionally consume the majority of an electrical engineer's design week — schematic capture, BOM assembly, and assembly documentation — can now be bootstrapped from a prompt. The engineer's value shifts decisively to the tasks that require physical judgment: EMC, signal integrity, power budgeting, debug, and the professional sign-off that no AI tool can stamp.
Source: @TimJayas on X, April 21 2026 — "NOW USE Claude Opus 4.7 to build electronics! … Generates wiring diagrams, Bills of materials, Step by step assembly guides … 100% free to try."
01Where your week actually goes (pre-augmentation)
Typical distribution for a mid-level electrical or electronics design engineer across product development, industrial controls, or embedded systems. Varies significantly by sector and project phase.
The first three segments — schematic, BOM, documentation — represent 65% of the week and are precisely what the April 2026 tool automates. The fourth segment, DRC and simulation, is partially automatable. What remains fully human: EMC and signal integrity judgment, physical bring-up and debug, safety and compliance sign-off, architecture decisions under uncertainty.
02Old role vs augmented role
- Draws schematics line by line in KiCad or Altium from a mental model of the circuit
- Assembles BOM by searching DigiKey and Mouser, entering parts manually
- Writes assembly and test documentation from scratch after design is locked
- Runs DRC manually; fixes violations; runs again
- Manages component obsolescence reactively — discovers the problem at BOM review
- Compiles design review packages manually across multiple tools
- Spends 3–5 days on documentation that manufacturing could have had on day 1
- Specifies circuit intent: interface requirements, voltage rails, signal paths, compliance constraints — AI generates the schematic
- Reviews AI-generated BOM for substitution risk, lead time, and functional equivalence
- Reviews and stamps assembly and test documentation generated alongside the design
- Validates DRC results and adjudicates AI-flagged violations with judgment
- Monitors component lifecycle continuously; acts on AI obsolescence flags before BOM is locked
- Owns design review presentation: narrates the engineering rationale behind AI choices
- Focuses primary time on signal integrity, EMC, power, and physical bring-up — the judgment work
03Day in the life — augmented electrical engineer
04New job description
Core accountabilities
- Own circuit intent: translate system requirements into voltage rails, signal paths, interface constraints, noise budgets, and compliance targets that AI can act on
- Review, validate, and adjudicate AI-generated schematics — document selection rationale with engineering basis
- Own signal integrity, EMC, and power budget decisions — these are not AI-delegatable in regulated or high-reliability designs
- Review AI-assembled BOMs for component risk, obsolescence, and functional equivalence of substitutes
- Own physical bring-up and debug — the bench is still human territory
- Sign compliance documentation; own the engineering argument in regulatory submissions
- Define the AI design review framework and intent-brief standards for the team
What no longer defines the role
- Originating schematics from scratch for well-understood circuit topologies
- Assembling BOMs manually from distributor searches
- Writing assembly and test documentation from scratch after design lock
- Running DRC passes manually and iterating without AI assistance
- Compiling design review packages across multiple disconnected tools
05KPIs that move
| Metric | Baseline | Augmented | Driver |
|---|---|---|---|
| Time from intent brief to first reviewable schematic | 3–8 days | 2–6 hours | AI schematic generation from structured intent brief |
| BOM assembly time per design | 1–3 days | 2–4 hours review | AI-assembled BOM; engineer reviews for risk and substitution |
| Assembly documentation ready at design lock | Days to weeks post-lock | Day of design lock | Documentation generated alongside schematic |
| Component obsolescence caught before BOM release | ~50% caught early | >95% caught early | Continuous lifecycle monitoring; proactive flag and substitute |
| DRC violations at first layout pass | 15–40 per design | 3–8 per design | AI pre-checks during schematic; fewer errors reach layout |
| Design variants evaluated per sprint | 1–2 topologies | 6–12 topologies | AI generates; engineer selects and adjudicates |
| EMC first-pass test success rate | ~35–50% | ~60–75% | AI EMC rule checking during design; earlier compliance consideration |
06Skills to develop
Circuit intent specification
Writing structured, AI-actionable design briefs: voltage budgets, signal path requirements, noise constraints, compliance targets. The new core competency — harder to articulate than it sounds.
AI schematic review
Critical reading of AI-generated schematics: identifying missing decoupling, unexpected topology choices, implicit assumptions about layout that the schematic doesn't show. Fast, systematic, engineering-rigorous.
Signal integrity and EMC depth
These stay human. Transmission line effects, crosstalk, return path management, EMC pre-compliance strategy — the skills that have always differentiated senior EEs become the new entry bar.
Physical bring-up and debug
Bench skills — oscilloscope, logic analyser, power sequencing, register-level debug — remain entirely human. These expand in importance as design volume per engineer increases.
Component risk literacy
Understanding substitution equivalence, JEDEC standards, lead-time exposure, and counterfeit risk. When AI flags a component, the engineer needs the depth to evaluate the proposed alternative intelligently.
Hardware-software boundary ownership
As schematic time contracts, the engineer who knows both the register map and the layout becomes the critical integration partner for firmware teams. This interface deepens, not shrinks.
07Junior and senior reshape
- Schematic-by-hand apprenticeship path is contracting — the repetitive seat time that built intuition now happens faster through AI review
- New entry ramp: writing intent briefs, validating AI schematics against requirements, owning physical bring-up for a sub-assembly
- EMC and signal integrity skills become primary earlier in career — no longer a senior specialisation
- BOM risk review and component qualification as real ownership, not clerical work
- Risk: engineers who arrive expecting schematic-by-hand experience will find the ramp changed; those who engage with AI review develop faster
- Domain expertise for writing intent briefs is now the scarcest resource on the team
- Cover more concurrent design programs — each no longer requires the same calendar time at the bench
- Own the AI design review framework: define what constitutes an acceptable AI-generated schematic for your product context
- Principal authority on EMC, power integrity, and compliance submissions — this is not delegatable
- Mentor juniors on critical AI review rather than on schematic origination
- Build the intent-brief library the team reuses across product families
08What percentage of your week could be augmented?
Adjust the sliders to match your actual weekly hours. The estimate reflects current AI capability, not theoretical future state.
of your week could move to autopilot or augmented review
Get the full Electrical Engineer transition playbook — new JD template, circuit intent-brief framework, AI schematic review checklist, and EDA tool shortlist — when we publish it.
09Frequently asked questions
Is the Electrical Engineer role going away?
No. Signal integrity judgment, EMC compliance ownership, physical test and debug, and the engineering sign-off on safety-critical systems all stay human. What moves to autopilot is schematic capture, BOM assembly, and documentation generation — work that previously consumed most of a design week. The role becomes higher-leverage, not redundant.
Does AI understand electrical safety and compliance requirements?
AI can flag UL, IEC, CE, and FCC requirements during design generation and check against known rule sets. But compliance sign-off is a human act. The engineer validates, interprets edge cases, and takes responsibility for the submission. AI reduces the compliance research burden substantially — it does not eliminate the compliance judgment.
What about high-voltage or safety-critical designs?
Higher consequence equals higher review burden, not exclusion from augmentation. The AI generates; the engineer applies more rigorous review and validation. The documentation trail from AI-generated designs is often better than manually assembled documentation because every decision is logged.
Will headcount drop in electrical engineering?
Individual engineers cover more concurrent design programs. In most organisations headcount holds while throughput grows 3–5×. Companies that cut headcount immediately typically discover the expertise needed to validate AI outputs and debug hardware failures isn't replaceable on short notice.
What EDA platforms does AI work with?
KiCad, Altium, Eagle, OrCAD, and Mentor Xpedition all have scriptable surfaces or API integrations that agentic tooling can address. The April 2026 Claude demos used Arduino and Raspberry Pi contexts, but the schematic generation logic extends to professional EDA platforms.
What happens to junior electrical engineers?
The schematic-capture apprenticeship path is contracting fast. Juniors who adapt focus on validating AI-generated designs, owning physical bring-up and debug, and building EMC and signal integrity skills earlier in their career. The new entry ramp is faster — meaningful work arrives sooner.
How does this interact with firmware and software teams?
The interface between hardware and software tightens. When the electrical engineer's job is reviewing AI-generated schematics and owning system integration, they spend more time at the hardware-software boundary — register maps, power sequencing, debug interfaces — which is exactly where firmware teams need a partner.
What's the fastest way to start?
Pick one well-understood sub-circuit — a power supply, a microcontroller breakout, a sensor interface — and ask an AI tool to generate the schematic, BOM, and bring-up guide. Spend an hour reviewing the output against your knowledge. The gaps in that review tell you exactly where the AI needs human judgment in your context.